Many digital and analog components and circuits have been successfully implemented in the silicon based integrated circuits. Such components include passive devices, such as resistors, capacitors, and inductors.
Implementing high quality factor (called high Q value) inductors that operate at high radio frequencies remains problematic in silicon-based very large scale integration (VLSI) integrated circuit semi-conductor chips. For microwave and wireless communications applications, it is desirable to integrate inductors and transformers monolithically on bulk silicon, silicon on insulator, or silicon on sapphire chips, Gallium-Arsenium or Germanium etc. For these applications, considerable innovation is necessary before adequate values of inductance as well as high Q values are obtained. The Q value of an inductor is given by the following equation:                               Q          =                      2            ⁢                                                   ⁢            π            ⁢                                                   ⁢                                          maximum                ⁢                                                                   ⁢                energy                ⁢                                                                   ⁢                stored                                            energy                ⁢                                                                   ⁢                dissipated                ⁢                                                                   ⁢                per                ⁢                                                                   ⁢                cycle                                                    ,                            (        1        )            
Most structures and methods used for fabricating high Q value inductors and transformers in hybrid circuits, monolithic microwave integrated circuits, or discreet applications (for example at larger dimensions, with better metals, on lossless substrates, etc.) are not readily compatible with silicon VLSI processing. U.S. Pat. No. 6,114,937 to Burghartz et al provides various references to conventional high Q value inductor fabrication methods.
Conventional inductors and transformers on silicon, which have strictly planer structures and are fabricated with conventional silicon fabrication processes and material, suffer from several limitations. First, conventional aluminum interconnect technology has a relatively high metal resistivity and limited metal thickness, both of which lead to a relatively high resistance of the spiral coil. The high resistivity lowers the quality factor Q, as seen from equation (1), because it contributes to the energy loss per cycle. Second, magnetic fields are strongly coupled to the silicon substrate, which is a lossy conductor with large skin depth even at radio frequencies. Induced currents in the silicon substrate act to oppose those in the spiral coil (the inductor) and cause what is known as the pinch effect (pinching off the current in the inductor), also lowering the Q value by contributing to the energy loss per cycle. In addition to the eddy currents in the substrate and the resulting pinch effect, neither of which are the focus of the present invention, in a planar inductor there are also currents induced in the metal windings of the planer spiral itself. Besides reducing the current in the spiral and so reducing the maximum energy stored per cycle and thus reducing the Q value of the spiral/inductor, the induced currents in the spiral dissipate energy stored in the windings (because they are an additional current flowing in a lossy medium, the coil material), with the result that, as shown by eq. (1), the Q value of the spiral is again reduced.
With a spiral inductor according to the prior art, portions of the innermost area of the spiral can actually have a negative current density (i.e. current in an opposite direction from the flow of the current overall). A negative current density occurs in the innermost branch of the spiral because the time-varying magnetic field is largest in the center turn of the spiral inductor. (More specifically, the current induced by the magnetic field caused by the current flowing in other parts of the spiral is strongest at the outer edge of the innermost turn of the spiral, and is in an opposite direction from the current in the rest of the spiral.)
To overcome some of the limitations of spiral inductors, toroidal inductors are used. Conventional multi-level interconnect technology allows fabrication of solenoidal or toroidal inductor structures instead of an inductor having a spiral configuration. Toroidal inductors have the benefit of confining the magnetic flux (to locations where there are no turns of the inductor), thereby minimizing substrate losses. However, conventional integrated toroidal inductors have comparably small inductance and Q values for a given silicon area relative to the planar spiral inductor configuration, because the area enclosed by wire windings of conventional toroidal inductors is small due to the limit in vertical dimensions of the thin films used in conventional VLSI processing.
Therefore, it is still advantageous in some respects to use a spiral inductor instead of a toroidal inductor, and it would be further advantageous to have a spiral inductor modified in a way that reduces induced currents in the spiral, i.e. in a way that reduces the tendency of current flowing in one part of the spiral to create a magnetic field through another part of the spiral, inducing currents there, and so reducing the net current there.